The present invention relates to electronic systems and circuits for use in wireless receivers and transmitters, and more particularly, to an electronic system having a mixer circuit with variable gain.
The field of wireless technology is currently undergoing a revolution, and is experiencing exponential growth. Cell phones, once considered a novelty and referred to as xe2x80x9ccar phonesxe2x80x9d are now ubiquitous, and cordless phones in the home are commonplace. A whole new batch of wireless personal digital assistants, and Bluetooth enabled computer peripherals are now entering the market, with wireless internet access as a driving force. A mixer having a variable gain is described which facilitates the design and lower the cost of circuits for these and other related products.
Wireless devices typically transmit and receive data through the air on high frequency electromagnetic waveforms, though some systems, such as satellite dishes and pagers simply receive, and others merely transmit. Data transmission is begun by encoding the data to be transmitted. This encoded data typically has a data rate of 100 kHz to 100 MHz and modulates a high frequency carrier signal. The carrier signal is often in the 2-10 GHz range. The modulated carrier signal is then applied to an antenna for broadcasting. The broadcast signal is referred to as a radio frequency (RF) signal. Reception involves receiving the RF signal on a different antenna, and filtering undesired spectral components. The signal is demodulated, filtered again, and decoded.
In real world situations, the amplitude of a received RF signal is constantly changing. For example, a passenger using a cell phone in a moving car may be traveling toward the antenna which is providing a signal. In that case, the amplitude of the received signal increases as the car approaches the antenna. Furthermore, buildings may intervene, or the car may enter a tunnel. These cause a received signal strength to decrease.
But receivers operate best if the amplitudes of received signals remain in a specific range. Specifically, if the signal power is too small, errors occur due to noise sources such as natural radiation, television and radio broadcasting, power transmission systems and the like. If the signal is too large, the linearity of the receive channel is lost and the signal begins to clip, again resulting in errors.
A conventional solution for this is to insert a variable gain amplifier in the receive channel. If the signal strength decreases, the amplifier gain is correspondingly increased. If received power increases, the gain may appropriately be lowered.
FIG. 1 is a block diagram of one such conventional receiver channel. Specifically, a direct conversion receiver is represented. It may also be referred to as a low IF (intermediate frequency), zero IF, or homodyne receiver. Included is a low noise amplifier (LNA) 110, a modulator or mixer 120, low pass filter (LPF) 130, variable gain amplifier (VGA) 140, analog to digital converter (A/D) 150, digital signal processor (DSP) 160, voltage controlled oscillator (VCO) 170, phase lock loop (PLL) 170, and digital to analog converter (D/A) 190. The PLL 160 includes a frequency synthesizer, phase-frequency detector, and loop filter.
The RF signal is received on an antenna (not shown) coupled to line 105. A choke filter may be used to remove unwanted spectral portions from received signal. The RF signal is amplified by LNA 110, and provided to the mixer 120. LNA 110 may be a composite of more than one amplifier, for example a second LNA may be on a chip with the other blocks shown, while a first LNA may be off-chip. A VCO 170 generates a local oscillator (LO) signal on line 175, and provides it to the mixer 120 and PLL 180. The VCO may be on-chip or off-chip; alternately it may have its transistors on-chip, with some passive components external.
The mixer 120 multiplies the RFin signal on line 115 with the LO signal on line 175. The mixer outputs a signal on line IF1125, which has spectral components at the two frequencies which are the sum and difference of the RFin and LO signals. Specifically, if the RFin and LO frequencies are both 2.4 GHz, IF1 has components at DC (0 Hz) and 4.8 GHz.
LPF 130 filters the high frequency sum products of IF1 while passing the low frequency difference components. VGA 140 adjusts the amplitude of the signal at IF3 in order to optimize the use of the dynamic range of A/D 150. The A/D 150 converts the analog signal IF3 on line 145 into a digital waveform, and provides it on bus DOUT 155 to DSP 160. The DSP 160 decodes the data, and provides an output on line 165. PLL 180 generates the voltage which controls the VCO""s oscillation frequency. The control voltage is Vtune, and is output from the PLL to the VCO on line 185. The PLL divides the LO signal on line 175 and compares that to a reference frequency (REF) provided on line 199. The LO frequency is adjusted accordingly.
DSP 160 provides a second output on bus Dgain 197. This signal is the result of a comparison of the amplitude of A/D output signal Dout on bus 155 with the range of available outputs from the A/D. The digital signal on Dgain bus 197 is converted to an analog signal used to control the gain of VGA 140. For example, one A/D may have 256 available output levels. If the signal at Dout 155 covers a range of only 30 levels, there is excessive quantization error. The gain of VGA 140 can be increased such that 200 levels are used. This increase in VGA gain results in a 4 times increase in the accuracy of the digitization of the waveform on IF3145. But if all 256 available output levels are used, the signal may be clipping, and information may be lost. The gain of VGA 140 can be reduced, again to where 200 levels are used.
A conventional mixer circuit used in conventional receivers and/or transmitters is shown in FIG. 2. The mixer has a first input port 245 labeled RFin, a second differential input port for the LO signal on lines 215 and 225, and a differential output signal IF1 on lines 265 and 275. Voltage changes at RFin generate a current in capacitor Cl 240. This current modulates the tail current provided by M3230 under the control of the bias voltage on node 235. This RFin modulated current is then multiplied in the mixer core M1210 and M2220, resulting in the IF1 output at nodes 265 and 275. The output signal IF1 will have two frequency components, one at the sum of the frequency of the RFin and LO signals, and one at the difference.
In FIG. 1, several blocks are involved in mixing the signals and adjusting the output amplitude. Specifically, mixer 120 mixes the signals, VGA 140 controls the signal amplitude, and DSP 160, along with D/A 190 control the gain of VGA 140. Each block adds noise to the signal, and consumes both power and die area. Moreover, the variation of gain in a typical VGA is often non-linear. Therefore, it would be desirable to obtain a mixer circuit that allows for a simpler topology with reduced complexity. Additionally, it would be desirable to obtain a system wherein the variable gain is substantially linear.
In accordance with embodiments of the present invention a simplified architecture for a receiver system is provided. Additionally, embodiments of the present invention provide a variable gain mixer circuit useful in the simplified receiver system.
Accordingly, one embodiment of the present invention provides an apparatus including a receiver system, the receiver system comprising a first amplifier having an input coupled to receive an input RF signal and an output to produce an amplified RF signal, a variable gain mixer circuit having a first input, a second input to receive the amplified RF signal, a mixer output, and a control input, a low pass filter coupled to the mixer output, an analog-to-digital converter coupled to the low pass filter for producing a digital output signal, and a voltage controlled oscillator for producing an oscillator signal, the oscillator signal coupled to the first input of the variable gain mixer circuit. The digital output signal is coupled to the control input of the variable gain mixer circuit for varying the gain of the mixer circuit.
Another embodiment of the present invention includes a mixer circuit comprising a mixer core receiving first and second inputs and having a plurality of output currents, a bias circuit coupled to the mixer core for providing a bias current, and a variable impedance network coupled to the plurality of output currents, wherein each of the plurality of outputs current is selectively coupled to a corresponding voltage output node through a variable impedance.
In one embodiment, the present invention includes a mixer circuit comprising a differential input stage for receiving a differential input signal and generating first and second differential output currents, a bias circuit having a bias output coupled to the differential input stage, the bias circuit receiving a bias signal, and in accordance therewith, generating a bias current at the bias output, and first and second variable impedance networks having corresponding first and second current input nodes, the first current input node coupled to the first differential output current and the second current input node coupled to the second differential output current, each variable impedance network including a digital input for receiving a digital control signal and a voltage output node. Each current input node is selectively coupled to a plurality of network nodes in the corresponding variable impedance network in accordance with the digital control signal, and each network node having a unique impedance to the corresponding voltage output node.
In one embodiment, the present invention includes a mixer circuit comprising first and second transistors for receiving a pair of differential input signals, a third transistor for receiving a modulated RF signal and for setting the DC bias current in the mixer, and a variable impedance network having a first terminal coupled to the first supply voltage and a second terminal coupled to a first current output of at least one of the first and second transistors. The variable impedance network further comprises a plurality of network nodes, a plurality of series resistors coupled between each of the network nodes each having a resistance R, a plurality of shunt resistors coupled between the network nodes and the supply voltage each having a resistance of 2R, a terminal shunt resistor coupled between a terminal network node and the supply voltage, and a plurality of switches for coupling the first current output to at least one of the network nodes.
In another embodiment, the present invention includes a method of controlling the gain in a mixer circuit comprising receiving first and second signals in a mixer core, receiving a bias current in the mixer core, generating a plurality of current outputs from the mixer core in response to the first signal, the second signal, and the bias current, receiving the plurality of current outputs in a variable impedance network, and selectively coupling each of the plurality of current outputs to a corresponding voltage output node through a variable impedance.
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the present invention.